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d a t a sh eet february 1994 integrated circuits philips semiconductors saa2022 tape formatting and error correction for the dcc system product speci?cation supersedes data of february 1993 file under integrated circuits, miscellaneous
philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 february 1994 2 features integrated error correction encoder/decoder function with digital compact cassette (dcc) optimized algorithms control of capstan servo during recording and after recording by microcontroller frequency and phase regulation of capstan servo during playback choice of two dynamic random access memory (dram) types operating in page mode scratch pad ram area available to microcontroller in system dram low power standby mode i 2 s interface microcontroller interface for high-speed transfer burst rates up to 170 kbytes per second sysinfo and auxiliary data flags on microcontroller interface protection against invalid auxiliary data +4 v operating voltage capability. general description performing the tape formatting and error correction functions for dcc applications, the saa2022 can be used in conjunction with the pasc (saa2002/saa2012), tape equalization (saa2032), read amplifier (tda1317 or tda1318) and write amplifier (tda1316 or tda1319) circuits to implement a full signal processing system. ordering information note 1. when using reflow soldering it is recommended that the dry packing instructions in the quality reference pocketbook are followed. the pocketbook can be ordered using the code 9398 510 34011. extended type number package pins pin position material code SAA2022GP 64 qfp (1) plastic sot208a
february 1994 3 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 block diagram mea711 - 2 microcontroller interface 28 29 2 tape input buffer tape output buffer sb ?i s 2 interface error correction coder dram interface 17?5 11?4 32 50 51 ltdata wdata wclock pino1 pino2 pino3 a0? d0? wen oen 10 16 43 8 27 59 v dd1 v dd2 v dd3 v dd4 1 64 63 30 31 52 ltref urda sbdir speed spdf azchk 55 mclk 58 26 7 42 ltclk 5 48 47 44 reset pwrdwn clk24 lten 6 ltcnt1 3 ltcnt0 49 pini 57 sbef 62 sbda 61 sbcl 60 sbws 56 sbmclk 4 33?1 tch0 - 7, taux clock generator control saa2022 v ss1 v ss2 v ss3 v ss4 rasn casn 9 15 fig.1 block diagram.
february 1994 4 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 pinning symbol pin description ltref 1 timing reference for microcontroller interface ltdata 2 data for microcontroller interface (3-state; cmos levels) ltcnt1 3 control for microcontroller interface ltcnt0 4 control for microcontroller interface ltclk 5 bit clock for microcontroller interface lten 6 enable for microcontroller interface v ss2 7 supply ground (0 v) v dd2 8 supply voltage (+5 v) rasn 9 dram row address strobe wen 10 dram write enable d3 11 dram data (msb); 3-state output; ttl compatible input d2 12 dram data; 3-state output; ttl compatible input d1 13 dram data; 3-state output; ttl compatible input d0 14 dram data (lsb); 3-state output; ttl compatible input casn 15 dram column address strobe oen 16 dram output enable a8 17 dram address (msb) a7 18 dram address a6 19 dram address a5 20 dram address a4 21 dram address a3 22 dram address a2 23 dram address a1 24 dram address a0 25 dram address (lsb) v ss3 26 supply ground (0 v) v dd3 27 supply voltage (+5 v) wclock 28 clock for write ampli?er transfers wdata 29 write ampli?er serial data speed 30 capstan phase information spdf 31 capstan frequency information pino1 32 port expander output 1 taux 33 aux channel input from saa2032 tch7 34 main data channel 7, input from saa2032 tch6 35 main data channel 6, input from saa2032 tch5 36 main data channel 5, input from saa2032 tch4 37 main data channel 4, input from saa2032 tch3 38 main data channel 3, input from saa2032 tch2 39 main data channel 2, input from saa2032
february 1994 5 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 tch1 40 main data channel 1, input from saa2032 tch0 41 main data channel 0, input from saa2032 v ss1 42 supply ground (0 v) v dd1 43 supply voltage (+5 v) clk24 44 24.576 mhz clock from saa2002 test0 45 test select lsb; do not connect test1 46 test select msb; do not connect pwrdwn 47 sleep mode selection reset 48 reset input with hysteresis and pull-down resistor pini 49 port expander input pino2 50 port expander output 2 pino3 51 port expander output 3 azchk 52 azimuth check (channels 0 and 7) test2 53 symbol error rate measurement output test3 54 do not connect mclk 55 master clock output (6.144 mhz) sbmclk 56 master clock for sb-i 2 s-interface sbef 57 byte error sb-i 2 s-interface v ss4 58 supply ground (0 v) v dd4 59 supply voltage (+5 v) sbws 60 word select sb-i 2 s-interface; 3-state output; cmos levels sbcl 61 bit clock sb-i 2 s-interface; 3-state output; cmos levels sbda 62 data line sb-i 2 s-interface; 3-state output; cmos levels sbdir 63 direction sb-i 2 s-interface urda 64 unusable data sb-i 2 s-interface symbol pin description
february 1994 6 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 20 21 22 24 25 26 27 28 29 30 31 32 23 64 63 62 60 59 58 57 56 55 54 53 52 61 ltref ltdata ltcnt1 ltcnt0 ltclk lten v ss2 v dd2 rasn wen d3 d2 d1 d0 casn oen a8 a7 a6 a5 a4 a3 a2 a1 a0 v ss3 v dd3 wclock wdata speed spdf pino1 taux tch7 tch6 tch5 tch4 tch3 tch2 tch1 tch0 v ss1 v dd1 clk24 test0 test1 pwrdwn reset pini pino2 pino3 azchk test2 test3 mclk sbmclk sbef v ss4 v dd4 sbws sbcl sbda sbdir urda saa2022 mea693 - 2 fig.2 pin configuration (sot208a).
february 1994 7 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 functional description heads and tape mea695 - 2 saa2022 ram 256 kbits saa2032 digital equalizer write read tda1317 or tda1318 tda1316 or tda1319 tape drive processing adc saa7360 dac saa7323 analog input daio tda1315 digital input analog output audio input/output pasc processing saa2012 saa2002 adaptive allocation and scale factors stereo filter codec recording + play back i s (sub-band) 2 microcontroller i s 2 speed control capstan drive digital output fig.3 dcc data flow diagram.
philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 february 1994 8 the saa2022 provides the following functions: in playback modes tape channel data and clock recovery 10 to 8 demodulation data placement in dram c1 and c2 error correction decoding i 2 s-interfacing to sb-i 2 s-bus interfacing to microcontroller for sysinfo and aux data capstan control for tape deck. in record modes i 2 s-interfacing to sb-i 2 s-bus c1 and c2 error correction encoding formatting for tape transfer 8 to 10 modulation interfacing to microcontroller for sysinfo and aux data capstan control for tape deck, programmable by microcontroller. operational modes the 3 basic modes of operation are: dpap - main data (audio) and sysinfo play, aux play drar - main data (audio) and sysinfo record, aux record dpar - main data (audio) and sysinfo play, aux record. hardware interfacing reset this is an active high input signal which resets the saa2022 and brings it into its default mode, dpap. this should be connected to the system reset, which can be driven by the microcontroller. the duration of the reset pulse should be at least 15 m s. this pin has an internal pull-down resistor of between 20 k w and 125 k w . pwrdwn this pin is an active high signal which places the saa2022 in a sleep mode. when the saa2022 is in sleep mode and the clk24 is either held high or held low, there is no activity in the device, thus resulting in no emi and a low power dissipation (typically <10% of operational dissipation). this pin should be connected to the dcc power-down signal, which can be driven by the system microcontroller. to enter the sleep mode the saa2022 should reset and hold reset. after a delay of at least 15 m s the pwrdwn pin should be brought high after which the state of the reset pin is dont care. the power dissipation is reduced further when the clk24 input signal stops. when recovering from sleep mode the pwrdwn pin should be driven low and the chip reset with a pulse of at least 15 m s duration. clk24 this is the 24.576 mhz clock input and should be connected directly to the saa2002 clk24 pin. connections to saa2032 tch0 to tch7 and taux these lines are the equalized and clipped (to v dd ) tape channel inputs and should be connected to the saa2032 pins tch0 to tch7 and taux. sub-band i 2 s-bus connections the timing for the sb-i 2 s-interface is given in figs 4 to 9.
february 1994 9 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 fig.4 sb-i 2 s-interface in playback master mode (1). sbda sbmclk sbcl sbws sbef bit number byte number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01 mea697 - 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 23 lines show rising edge of sbmclk 23 01 byte number
february 1994 10 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 fig.5 sb-i 2 s-interface in playback master mode (2). mea696 t dsr t dsr sbmclk (input) t l-1 t h-1 sbcl (output) sbws (output) sbef (output) sbda (output) t dmr sbef (output) mclk (output) t sumr t sumr
february 1994 11 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 fig.6 sb-i 2 s-interface in playback slave mode (1). sbda sbcl sbws sbef bit number byte number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01 mea699 - 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 23
february 1994 12 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 fig.7 sb-i 2 s-interface in playback slave mode (2). mea698 t sumr t hmr t hmr sbcl (input) sbws (input) sbef (output) sbda (output) t dmr t sumr mclk
february 1994 13 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 fig.8 sb-i 2 s-interface in record mode (1). sbda sbcl sbws bit number byte number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01 msa536 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 23
february 1994 14 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 fig.9 sb-i 2 s-interface in record mode (2). mea700 mclk (output) t sumr sbcl (input) sbws (input) sbda (input) t hmr
philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 february 1994 15 sbmclk this is the sub-band master clock input for the sb-i 2 s-interface. the frequency of this signal is nominally 6.144 mhz. this pin should be connected to the sbmclk pin of the saa2002. sbdir this output pin is the sub-band i 2 s-bus direction signal, it indicates the direction of transfer on the sb-i 2 s-bus. a logic 1 indicates a saa2022 to saa2002 transfer (audio play) whilst a logic 0 is output for a saa2002 to saa2022 transfer (audio record). this pin connects directly to the sbdir pin on the saa2002. sbcl this input/output pin is the bit clock line for the sb-i 2 s-interface to the saa2002. is has a nominal frequency of 768 khz. sbws this input/output pin is the word select line for the sb-i 2 s-interface to the saa2002. it has a nominal frequency of 12 khz. sbda this input/output pin is the serial data line for the sb-i 2 s-interface to the saa2002. sbef this active high output pin is the error per byte line for the sb-i 2 s-interface to the saa2002. urda this active high output pin indicates that the main data (audio), the sysinfo and the auxiliary data are not usable, regardless of the state of the corresponding reliability flags. the state of this pin is reflected in the urda bit of status byte 0, which can be read by the microcontroller. this pin should be connected directly to the urda pin of the saa2002. urda is activated as a result of a reset, a mode change from drar to dpap, or if the saa2022 has had to resynchronize with the incoming data from tape. the position of the first sb-i 2 s-bytes in a tape frame is shown in fig.10.
february 1994 16 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 fig.10 position of first sb-i 2 s-bytes in tape frame. mode dpap or dpar sbda sbws ltref byte number 8191 byte number 2 byte number 1 byte number 0 mea701 - 2 mode drar sbda sbws ltref byte number 2 byte number 1 byte number 0 byte number 8191 of previous tape frame 0 1 3 0 snum snum of previous tape frame
february 1994 17 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 fig.11 dram timing read cycle. mea702 mclk rasn casn d0...d3 a0...a7 (a8) oen wen 1 read cycle = 651 ns row column #0 column #1 column #2 #1 #2 #0 dram interface the saa2022 has been designed to operate with 64 k 4-bit or 256 k 4-bit drams operating in page mode, with an access time of 80 to 100 ns. the timing for read, write and refresh cycles is shown in figs 11 to 13. casn this output pin is the column address strobe (active low) for the dram, it connects directly to the column address strobe pin of the dram. rasn this output pin is the row address strobe (active low) for the dram, it connects directly to the row address strobe pin of the dram. oen this pin provides the output enable (active low) for the dram, it connects directly to the output enable pin of the dram. wen this output pin provides the write enable (active low) for the dram, it connects directly to the write enable pin of the dram. a0 to a8 these output pins are the multiplexed column and row address lines for the dram. when the 64 k 4-bit dram is used, pins a0 to a7 should be connected to the dram address input pins, and pin a8 should be left unconnected. when using the 256 k 4-bit dram then address pins a0 to a8 should be connected to the address input pins of the dram.
february 1994 18 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 mea703 mclk rasn casn d0...d3 a0...a7 (a8) oen wen 1 write cycle = 651 ns row column #0 column #1 column #2 #1 #2 #0 fig.12 dram write cycle. d0 to d3 these input/output pins are the data lines for the dram, they should be connected directly to the dram data i/o pins. write ampli?er interface the saa2022 may be used with either the tda1316 or tda1319 write amplifiers. wclock this output pin provides the 3.072 mhz clock output for the write amplifier, it should be connected directly to the wclock pin of the write amplifier. wdata this output pin is the multiplexed data and control line for the write amplifier (timing information is shown in fig.14). the wdata pin should be connected directly to the wdata pin of the write amplifier.
february 1994 19 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 fig.13 dram refresh cycle. mea704 - 1 mclk rasn casn d0...d3 a0...a7 (a8) oen wen 1 refresh cycle = 651 ns row tape deck capstan control interface speed this signal is a pulse width modulated output that may be used to control the tape deck capstan. the period of the speed signal is 41.66 m s and the nominal duty cycle is 50%. there are 4 modes of operation for the speed signal which can be selected by the programmed settings of m cspd (microcontroller capstan speed), enfreg (enable frequency regulation) and enefreg (enable extended frequency regulation) flags. spdf if m cspd = logic 0 this pin outputs a pulse width modulated measurement of the main data channel bit rates and may be used in combination with the speed signal to control the tape deck capstan. the period of the spdf signal is 5.2 m s. the duty cycle of spdf can vary from 0% at +6.5% deviation to 100% at - 6.5% deviation. if the deviation = 0% then the duty cycle of spdf is 50%. microcontroller interface ltref the saa2022 divides time into segments of 42.67 ms nominal duration which are counted in modulo 4. the ltref active low output pin can be connected directly to the interrupt input of the microcontroller and indicates the start of a time segment. it goes low for 5.2 m s once every 42.66 ms and can be used for generating interrupts. note if a resync occurs then the time between the occurrences of ltref can vary. the function and programming of the other interface lines ltcnt0, ltcnt1, lten, ltclk and ltdata are described in the pinning and programming sections.
february 1994 20 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 mla643 wclock wdata sync tdatplb tauxplb teraux tch0 tch1 tch2 tch3 tch4 tch5 tch6 tchaux tch7 sync tdatplb fig.14 wdata and wclock timing.
february 1994 21 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 fig.15 azchk timing. h andbook, full pagewidth mea705 (8 periods mclk) 1.3 m s this is a measure of the azimuth error. duration of the one tape block 5.3 ms azchk test pins test0, test1, test2 and test 3 these input pins are for test use only and for normal operation should not be connected. azchk this output pin indicates the occurrence of a tape channel sync symbol on tape channels tch0 and tch7. the separation between the pulses for the tch0 and tch7 channels gives a measure of the azimuth error between the tape and head alignment (see fig.15). port expansion pins pini this input pin is connected directly to the pini bit in the status byte 1, it can be read by the microcontroller, and may be used for any cmos level compatible input signals. pino1 this output pin is connected directly to the pino1 bit of the settings byte 1 register and can be set or reset by the microcontroller. pino2 this output pin is connected directly to the pino2 bit of the settings byte 1 register and can be set or reset by the microcontroller. pino3 this output pin is connected directly to the pino3 bit of the settings byte 1 register and can be set or reset by the microcontroller. power supply pins v dd1 to v dd4 these are the +5 v power supply pins which must all be connected. decoupling of v ss1 to v ss4 is recommended. v ss1 to v ss4 these are the +5 v power supply ground pins, all of which must be connected.
february 1994 22 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 programming the saa2022 via the microcontroller interface table 1 saa2022 interface connections to the microcontroller. all transfers are in units of 8-bits, registers with less than 8-bits are lsb justified, unless otherwise specified. the four basic types of transfer are shown in table 2. table 2 types of transfer. microcontroller interface registers the saa2022 microcontroller interface has 7 write and 4 read registers, as shown in table 3. table 3 saa2022 microcontroller interface registers. pin input/output description lten i enable active high ltclk i clock signal ltcnt0 i control lsb ltcnt1 i control msb ltdata i/o bi-directional data ltref o timing reference 5 m s at start of every segment active low ltcnt1 ltcnt0 transfer explanation 0 0 wdat write data to saa2022 0 1 rdat read data from saa2022 1 0 wcmd write command to saa2022 1 1 rstat read status from saa2022 register read/write no. of bits comments set0 write 7 primary settings set1 write 8 secondary settings cmd write 6 microcontroller command bytcnt write 8 byte counter raccnt write 7 random access counter spddty write 8 duty cycle for speed aflev write 4 auxiliary ?ag level status0 read 8 primary status status1 read 7 secondary status status2 read 8 sysinfo/aux ?ags status3 read 8 channel status ?ags
february 1994 23 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 direct access only one write (cmd) and four read (status0 to status3) registers can be directly accessed using the ltcnt lines, all other registers must be accessed by first programming the command register. the four status registers can be read by performing 4 rstat transfers within the same lten = high period. indirect access to write to or read from the indirect access registers, a command must first be sent to the command register. the transfer of bytes can then occur using wdat and rdat type transfers. it is the responsibility of the microcontroller to ensure that the transfer type and the last command are compatible. the same type of transfer can continue until a new command is sent. typical transfers on the microcontroller interface are shown in figs 16 to 19. fig.16 lt interface timing (1). mea715 - 1 lten ltcnt0,1 ltclk ltdata lten ltcnt0,1 ltclk ltdata 0 1 2 3 4 5 6 7 t su3 t h3 t su2 t su4 t su1 t h1 t le t lc t hc t h2 0 t d1 t su2 t su4 t su1 t h1 t le t lc t hc t h2 1 2 3 4 5 6 7 t h6 t d2 t h5 transfer of byte from microcontroller (a) transfer of byte to microcontroller (b)
february 1994 24 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 notes to fig.16a. note 1. see interface timing (fig.16b) for the transfer of a byte to the microcontroller. description timing for the timing ?gures it is assumed that cycle time t cy of mclk is within the limits 160 ns < t cy < 165 ns the set-up time t su of lten, ltcnt, ltclk and ltdata to mclk high t su <40ns the hold time t h of lten, ltcnt, ltclk and ltdata to mclk high t h = 0 ns lten low time before start data transfer t le > 535 ns; note 1 ltclk low time t lc > 205 ns ltclk high time t hc > 205 ns ltcnt0/1 set-up time to lten high t su1 > 205 ns ltcnt0/1 hold time to lten high t h1 > 205 ns lten set-up time to ltclk low t su2 > 0 ns lten hold time to ltclk high t h2 > 205 ns ltdata set-up time to ltclk high t su3 > 205 ns ltdata hold time to ltclk high t h3 > 40 ns ltclk set-up time to lten high t su4 > 535 ns
february 1994 25 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 notes to fig.16b. note 1. t le is determined by the longest path from lten low to ltdata. this path is via the reset of the internal bit counter. this reset is only necessary when after the last lten = low, an exact multiple of 8-bits has not been transferred. otherwise t le can be t cy = 165 ns less. description timing for the timing ?gures it is assumed that cycle time t cy of mclk is within the limits 160 ns < t cy < 165 ns the set-up time t su of lten, ltcnt, ltclk and ltdata to mclk high t su <40ns the hold time t h of lten, ltcnt, ltclk and ltdata to mclk high t h = 0 ns the delay time t d of ltdata from mclk high is within the limits 0 ns < t d <30ns the delay time t d of lten to the 3-state control of ltdata 0 ns < t d <50ns lten low time before start data transfer t le > 535 ns; note 1 ltclk low time t lc > 205 ns ltclk high time t hc > 205 ns ltcnt0/1 set-up time to lten high t su1 > 205 ns ltcnt0/1 hold time from lten high t h1 > 205 ns lten set-up time to ltclk low t su2 > 0 ns lten hold time from ltclk high t h2 > 205 ns ltclk set-up time to lten high t su4 > 535 ns ltclk hold time from lten low t h5 > 160 ns ltdata hold time from lten low t h6 > 0 ns ltdata delay time from lten high t d1 < 235 ns ltdata delay time from ltclk high t d2 < 400 ns ltdata delay time from lten (3-state control) t d4 < 50 ns
february 1994 26 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 0 1 2 3 4 5 6 0 7 1 2 3 4 5 6 0 7 1 2 3 4 5 6 7 t d3 t d3 status byte 2 status byte 1 status byte 0 3hex lten ltcnt0,1 ltclk ltdata 0 1 2 3 4 5 6 7 t ds1 t ds2 0 1 2 3 4 5 6 0 7 1 2 3 4 5 6 7 second sysinfo byte first sysinfo byte command rdsys 2hex lten ltcnt0,1 ltclk ltdata 10010000 1hex mea712 - 1 0 1 2 3 4 5 6 7 t dr1 0 1 2 3 4 5 6 0 7 1 2 3 4 5 6 7 second sysinfo byte first sysinfo byte command wrsys 2hex lten ltcnt0,1 ltclk ltdata 11010000 0hex t dr2 transfer of 2 sysinfo bytes to microcontroller (in fast transfer period) transfer of 3 status bytes to microcontroller transfer of 2 sysinfo bytes from microcontroller (in fast transfer period) fig.17 lt interface timing (2).
february 1994 27 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 mea714 2hex 0hex 2hex 1hex lten ltcnt0,1 ltclk ltdata idbyte 08hex rdsys sysinfo (8) sysinfo (9) 2hex 0hex 2hex lten ltcnt0,1 ltclk ltdata idbyte 08hex wrsys 0hex sysinfo (8) sysinfo (9) transfer of two sysinfo bytes starting at byte # 8 to microcontroller (in fast transfer period) transfer of two sysinfo bytes starting at byte # 8 from microcontroller to saa2022 (in fast transfer period) 0hex 1hex fig.18 lt interface timing (3).
february 1994 28 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 mea713 2hex 0hex 2hex 0hex 2hex 1hex 1hex lten ltcnt0,1 ltclk ltdata idbyte 97hex l 38hex rddrac spr (3,5,23) spr (3,5,24) 2hex 0hex 2hex 0hex 2hex lten ltcnt0,1 ltclk ltdata idbyte 97hex 38hex wrdrac 0hex 0hex spr (3,5,23) spr (3,5,24) transfer of two scratch pad ram bytes (spr) starting at spr page 3, column 5, row 23 to microcomputer (in fast transfer period) transfer of two scratch pad ram bytes (spr) starting at spr page 3, column 5, row 23 from microcontroller to saa2022 (in fast transfer period) draccnt l draccnt fig.19 lt interface timing (4).
february 1994 29 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 mea717 100 % 91 % 50 % 9 % 0 duty factor speed + 2 blocks + 10.6 ms + 1.65 blocks + 8.8 ms ?2 blocks ?10.6 ms ?1.65 blocks ?8.8 ms 0 fig.20 speed pulse width as a function of phase error. mea706 snum auxblk sysblk 01 2 3 0123012301 23012301230123 23 01 0123 0123 23 0123 0 1 0123 2 0 0123 0123 0123 0 2 0123 0123 0123 0123 0 123 0123 aux chn reclab data chn fig.21 recording a label.
february 1994 30 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 table 4 microcontroller interface commands. cmd register 76543210 command explanation xxxx1000 rdaux read auxiliary info xxxx1001 rdsys read sysinfo xxxx1010 wraux write auxiliary info xxxx1011 wrsys write sysinfo xxxx0000 ldset0 load new settings register 0 xxxx0001 ldset1 load new settings register 1 xxxx0010 ldaflev load aux ?ag threshold level xxxx0011 ldspddty load record speed duty cycle xxxx0101 ldbytcnt load byte counter xxxx0110 ldraccnt load random access counter xxyz1100 rddrac read data in random access mode from ram quarter yz xxyz1101 rdfdrac read ?ag and data in random access mode from ram quarter yz xxyz1110 wrdrac write data in random access mode to ram quarter yz xxyz1111 wrfdrac write ?ag and data in random access mode to ram quarter yz explanation of settings set0 r egister (t able 6) m cspd an active high, selects microprocessor control for the speed pulse width modulated servo control signal. disrsy disable resyncs active high, is used in after recording. reclab record labels active high when in drar or dpar modes; a label being defined as the bodies of all four aux tape blocks in a tape frame which is being written. this setting has immediate effect and should only be modified in time segment 1. enfreg in modes dpap and dpar enable frequency regulation active high, allows frequency information from the data channels to be used with the phase information to generate the capstan speed signal. enefreg enable extended frequency regulation active high, allows extended frequency information from the data channels to be used with the normal frequency information and the phase information to generate the capstan speed signal, if enfreg is active. set1 r egister (t able 7) test1 this setting is for test only. for use in applications this bit should be always programmed to logic 0. pino1 pin output 1, port expander output for the microcontroller. tfemas this allows the saa2022 to become master of the sb-i 2 s-bus in modes dpap and dpar. in mode drar the device always operates as a slave irrespective of the settings bit.
philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 february 1994 31 portab portable application active high, allows for the data channels clock extraction to track fast variations in tape bit rate. for home use set to inactive. nocos no corrected output symbol active high, disables the writing of the error corrected output to the dram. it is only used for debugging. test2 this setting is for test only. for use in applications this bit should always be programmed to logic 0. pino2 pin output 2, port expander output for the microcontroller. pino3 pin output 3, port expander output for the microcontroller. t ape p hase m ode enfreg = logic 0, enefreg = logic 0 and m cspd = logic 0 in this mode the saa2022 performs a new calculation to determine the pulse width for the speed signal approximately once every 21.33 ms, giving a sampling rate of approximately 46.9 hz. this calculation is basically a phase comparison between the incoming main data tape frame and an internally generated reference. the pulse duty cycle increases linearly from approximately 9% when the incoming main data tape frame is 1.65 tape blocks (8.8 ms) too early up to 91% when the incoming main data tape frame is 1.65 tape blocks (8.8 ms) too late, in 256 steps (see fig.20). outside 2 tape blocks range the pulse width characteristic overflows and repeats itself forming a saw-tooth pattern. the saa2022 has an internal buffer of 8.8 ms inside which the phase information is valid. t ape f requency m ode enfreg = logic 1, enefreg = logic 0 and m cspd = logic 0 the above description is overridden with frequency information. that is if the incoming main data bit rate deviates by more than approximately 6% from the nominal bit rate of 96000 bits per second, frequency information is mixed with the phase information. in between the limits 6% the pulse width is determined as above. e xtended t ape f requency m ode enfreg = logic 1, enefreg = logic 1 and m cspd = logic 0 in this mode there are 3 regions. this provides a more gentle transition from frequency plus phase control to phase only control. firstly from 0% to 4.5% deviation, where the operation is as for the tape phase mode. secondly from 4.5% to 6% deviation where the contribution of the frequency information to the servo information is half of that in the region beyond 6% deviation. thirdly when the deviation is greater than 6%, which is the same as for the tape frequency mode. m icrocontroller m ode m cspd = logic 1 in this mode the pulse width is determined by the microcontroller programming of the spddty interface register. nmode0, nmode1 these two bits control the mode change operation in the saa2022. table 5 nmode1, nmode0. nmode1 nmode0 operating mode 0 0 dpap 1 0 dpar 1 1 drar 0 1 invalid state
february 1994 32 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 s ettings r egisters table 6 set0. table 7 set1. setting bit default enefreg 6 0 enfreg 5 0 reclab 4 0 disrsy 3 0 m cspd 2 0 nmode1 1 0 nmode0 0 0 setting bit default pino3 7 0 pino2 6 0 test2 5 0 nocos 4 0 portab 3 1 tfemas 2 1 pino1 1 0 test1 0 0 table 8 speed source. notes 1. tape means that the duty cycle has been calculated from the playback tape signal. 2. m c means that the microcontroller programs the duty cycle via the spddty register in the microcontroller interface. 3. 50% defines that the duty cycle is fixed at 50%. mode m cspd speed dpap 0 tape (1) dpap 1 m c (2) dpar 0 tape (1) dpar 1 m c (2) drar 0 50% (3) drar 1 m c (2) table 9 typical settings. setting byte when 01 7654321076543210 x 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 play home machine x 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 play portable machine x x x 0 x 0 1 1 0 0 0 0 0 1 0 0 record no label x x x 1 x 0 1 1 0 0 0 0 0 1 0 0 record label x x x 0 1 1 1 0 0 0 0 0 0 1 0 0 after record no label x x x 1 1 1 1 0 0 0 0 0 0 1 0 0 after record label
february 1994 33 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 s tatus r egisters the saa2022 has 4 status registers all of which are read only. a circular pointer is used to select which of the status registers is addressed. this pointer is reset to point to status0 as result of the rising edge of lten while the ltcnt0/ 1 = rstat. any number of the registers may be read, always starting at status0. table 10 status0. table 11 status1. status bit bit rfbt 7 sysflc 6 auxflc 5 auxflo 4 flagi 3 urda 2 snum1 1 snum0 0 status bit bit slowtfr 7 test4 6 - 5 pini 4 pag2 3 pag1 2 mode1 1 mode0 0 table 12 status2. table 13 status3. status bit bit nflg3 7 nflg2 6 nflg1 5 nflg0 4 flg3 3 flg2 2 flg1 1 flg0 0 status bit bit chans7 7 chans6 6 chans5 5 chans4 4 chans3 3 chans2 2 chans1 1 chans0 0
philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 february 1994 34 snum0, snum1 time segment number. urda unreliable data active high, means that regardless of the other flag information you cannot use the data, sysinfo or aux, because they are unreliable , this can occur as result of a resync, a mode change from mode drar to mode dpap, or a reset of the saa2022. when a resync occurs it resynchronizes with the incoming main data tape channel information, with a result that for a period of time, the time that urda is high all output data is unusable. flagi instantaneous flag active high, indicates that the auxiliary byte that is about to be transferred to the microcontroller has a flag that is 3 aflev, or that the sysinfo byte that is about to be transferred is in error. auxflo old aux flag active high, indicates that auxiliary data due to be transferred to the microcontroller in the current segment should not be used. auxflc aux flag active high, indicates that at least one of the auxiliary data bytes due to be transferred to the microcontroller in the current segment is in error. this information is provided before the transfer occurs. sysflc sysinfo flag active high, indicates that at least one of the sysinfo bytes in the current segment is in error. this information is provided before the transfer occurs. rfbt ready for byte transfer of sysinfo, aux or scratch pad ram to or from the microcontroller active high. mode0, mode1 current mode of operation of the saa2022. pag1, pag2 two most significant bits of the modulo 6 internal page counter, the least significant bit is equal to snum0. pini pin input, port expander input for the microcontroller. test4 this is for test purposes only. slowtfr indicates that lt data transfers of sysinfo, aux or scratch pad ram can only occur at low speed rate. this occurs only during the second half of time segment 0, therefore the status bit rfbt must be polled to see if a transfer is possible. this bit will be high only during the second half of time segment 0. flg 0 to 3 error flag from the next auxiliary/sysinfo byte which is to be transferred to the microcontroller. the flags for sysinfo bytes have only 2 values, logic 0 which implies that the error corrector finds the bytes are good and logic 1 which implies that the bytes are in error. the flags for auxinfo bytes can have any one of 16 values, 0 to 15, depending on the type of correction. all of the aux bytes in the same aux code word will have the same flag value. the less reliable the data, the higher the flag value. it is recommended that any byte with a flag value of 10 or higher is deemed unreliable. nflg 0 to 3 error flag from the byte after the next auxiliary/ sysinfo byte which will be transferred to the microcontroller. chans 0 to 7 error correction channel status, which indicates if the even c1 code words in the 5th block of the segment for each data tape channel were non correctable. therefore 1 in every 16 c1 code words from each channel is monitored to see if the c1 error correcting decoding was successful.
february 1994 35 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 loadable registers table 14 aflev. aux flag threshold level. flagi goes high for the aux bytes whose flags are 3 aflev. auxflc will go high if the flags from either code word in the current segment are 3 aflev. the default value is 10. table 15 spddty. speed duty cycle register. if m cspd is active, this register determines the duty cycle of the speed signal. the duty cycle is given by: 0 for 0% duty cycle 128 for 50% duty cycle 255 for 99.6% duty cycle. the default value is 128. table 16 bytcnt. byte counter for sysinfo, aux and scratch pad ram transfers. for sysinfo: values 0 to 31 access sysinfo from the current segment. values 32 to 63 access sysinfo from the current +1 segment. values 64 to 95 access sysinfo from the current +2 segments. values 96 to 127 access sysinfo from the current +3 segments. in random access mode the system address is mapped on to bytcnt as follows: table 17 system addres in random access mode. table 18 raacnt. 3210 bit 1 0 1 0 default value 76543210 bit 10000000 default value 76543210 bit 00000000 default value 76543210 bytcnt 76543210row 6543210 bit 0000000 default value duty cycle spddty 100 256 ------------------------------------------ = %
february 1994 36 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 random access counter is used for generating addresses in the random access mode, the system address is mapped on to raccnt as shown in table 19. table 19 system address. 6543210 raccnt ------ 8 row --- 210 - col 210 ---- pag sysinfo and aux data offsets aux data consists of 4 blocks of 36 bytes, one block being transferred in each time segment. each tape frame contains 128 bytes of sysinfo, the sysinfo bytes can for convenience, be considered as being grouped into 4 sysinfo blocks, with: sysblk0 ==> si0 to si31, sysblk1 ==> si32 to si63, etc. in modes dpap and dpar sysinfo transfers may occur in two ways: 1. 4 blocks of 32 bytes, one block being transferred from the saa2022 in each time segment. 2. 1 block of 128 bytes being transferred in time segment 1. in mode drar sysinfo must be transferred to the saa2022 as 4 blocks of 32 bytes, one block in each segment. figures 26 to 29 show the offsets between the sysinfo and aux and the time segment counter, for the various modes of operation of the saa2022.
february 1994 37 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 b lock offsets with respect to time segment mode dpap sysblk = (snum + 3) mod 4; or read all 4 sysinfo blocks when snum = 1. if aux and main were recorded simultaneously then auxblk = (snum + 1) mod 4; else read and interpret 1 aux block in each time segment. mode drar sysblk = snum; auxblk = (snum + 1) mod 4. mode dpar sysblk = (snum + 3) mod 4; or read all 4 sysinfo blocks when snum = 1; auxblk = (snum + 1) mod 4. t he s cratch p ad ram the saa2022 provides the microcontroller with a scratch pad ram, which it can use for any purpose. the size of the scratch pad depends upon the size of the dram used and the locations may be written and read in 8-bit or 12-bit units. for a 64 k 4-bit dram, the scratch pad is arranged as 6 pages, where each page consists of 7 columns 64 rows. the pages are numbered 0 to 5, columns 1 to 7 and rows 0 to 63. this gives a total of (6 7 64) = 2688 locations. for a 256 k 4-bit dram, the scratch pad is the same as for the 64 k 4 bit dram, plus an additional 3 ram quarters, each of 6 pages where each page consists of 8 columns 448 rows. the pages are numbered 0 to 5, columns 0 to 7 and rows 0 to 431. this gives then a total of (2688 + (3 6 8 448)) = 67200 locations. the ram quarter is chosen by the yz bits of the microcontroller interface commands. use of the scratch pad ram outside the above ranges will upset the operation of the device. as with sysinfo, aux transfers can occur at high-speed at all times except the second half of time segment 0, that is when the status bit slowtfr is high. during this period the microcontroller must poll the status bit rfbt to determine when a transfer can occur. there are two possible methods for addressing the scratch pad ram. for random access of the scratch pad the address of each location is sent by the microcontroller to the saa2022 before each location transfer. alternatively, the address of the first location can be sent by the microcontroller before the first location transfer. this will automatically increment the row for all subsequent transfers until the end of the column. the raccnt and bytcnt registers are used for addressing the scratch pad. for the 64 k 4-bit dram, and first quarter of 256 k 4 dram the mapping of the scratch pad ram address onto the raccnt and bytcnt registers is shown in tables 20 and 21. for the other three-quarters of the 256 k 4 dram the mapping of the scratch pad ram address onto the raccnt and bytcnt registers is shown in tables 22 and 23. table 20 raccnt bit. table 21 bytcnt bit. raccnt bit 6543210 p2 p1 p0 c2 c1 c0 1 bytcnt bit 76543210 1 0 r5 r4 r3 r2 r1 r0 table 22 raccnt bit. table 23 bytcnt bit. raccnt bit 6543210 p2 p1 p0 c2 c1 c0 r8 bytcnt bit 76543210 r7 r6 r5 r4 r3 r2 r1 r0
february 1994 38 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 mode changes table 24 possible mode changes for the saa2022. current mode new mode dpap drar dpar dpap - yes yes drar yes -- dpar yes -- t iming for m ode c hanges mode change dpap to drar this mode change occurs at the end of the time segment in which the saa2022 receives the new settings. writing of the first main and aux data commences at the start of the time segment 1 which follows two subsequent end of time segment 3 intervals. the delay to writing to tape is approximately 222 ms, as shown in fig.22. if seamless appending is required the new settings should be sent to the saa2022 during time segment 2. mode change dpap to dpar this mode change occurs at the first end of time segment 2 after the saa2022 receives the new settings. output of aux to tape begins at the start of the following time segment 1, (i.e. ? 85.3 ms after the mode change), as shown in fig.23. mode change drar to dpap this mode change occurs at the first end of time segment 0 after the saa2022 receives the new setting. writing of main and aux data stops immediately after the mode change. the time segment jumps back to 0, urda goes high and stays high for 5 time segments ( ? 213.3 ms) after which it goes low, as shown in fig.24. mode change dpar to dpap this mode change occurs at the first end of time segment 0 after the saa2022 receives the new setting. the writing of aux data to tape stops immediately after the mode change. the first aux read from tape can be expected during the following time segment 0 or 1 (i.e. 128 to 170.67 ms after the mode change), as shown in fig.25.
february 1994 39 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 fig.22 mode change dpap to drar (aux and main simultaneously recording). handbook, halfpage mea707 - 2 snum mode 01 23 0123012 new mode auxiliary, main tape out dpap drar ? 222 ms drar fig.23 mode change dpap to dpar (aux after recording). handbook, halfpage mea708 - 2 snum mode 123 0123012 new mode auxiliary tape out dpap dpar ? 85.3 ms dpar fig.24 mode change drar to dpap. handbook, halfpage mea709 - 1 snum mode 123 0 12301 new mode urda drar dpap ? 213.3 ms dpap 0 fig.25 mode change dpar to dpap. handbook, halfpage mea710 - 2 snum mode 123 0123012 new mode auxiliary tape out dpar dpap ? 128 ms dpap ? 170.66 ms auxiliary to microcontroller
february 1994 40 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 mlb413 snum aux blk 01 2 3 0123012 sys blk aux, main data input from tape 3012 123 0123012 30 123 3 0123012 3012 2301 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 01 2 3 0123012 3012 sys blk * fig.26 sysinfo and aux block delays in dpap (audio and aux simultaneously recorded). mlb414 snum aux blk 01 2 3 0123012 sys blk aux, main data input from tape 3012 3 0123012 3012 2301 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 01 2 3 0123012 3012 sys blk * depends on phase of aux wrt main data channels fig.27 sysinfo and aux block delays in mode dpap (audio and aux recorded separately).
february 1994 41 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 mlb415 snum aux blk 01 2 3 0123012 sys blk aux, main data output from tape 3012 123 0123012 30 123 3 0123012 3012 2301 01 2 3 0123012 3012 fig.28 sysinfo and aux block delays in mode drar. mlb416 snum aux blk 01 2 3 0123012 sys blk main data input from tape 3012 123 0123012 30 123 3 0123012 3012 2301 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 01 2 3 0123012 3012 sys blk * 1 0123012 3012 2301 aux output to tape fig.29 sysinfo and aux block delays in mode dpar.
february 1994 42 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. input voltage should not exceed 6.5 v unless otherwise specified. 2. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. 3. equivalent to discharging a 200 pf capacitor through a 0 w series resistor. dc characteristics v dd = 3.8 to 5.5 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage - 0.5 +6.5 v v i input voltage note 1 - 0.5 v dd + 0.5 v i ss supply current in v ss -- 100 ma i dd supply current in v dd - 100 ma i i input current - 10 +10 ma i o output current - 20 +20 ma p tot total power dissipation - 500 mw t stg storage temperature - 55 +150 c t amb operating ambient temperature - 40 +85 c v es1 electrostatic handling note 2 - 1500 +1500 v v es2 electrostatic handling note 3 - 70 +70 v symbol parameter conditions min. typ. max. unit supply v dd supply voltage note 1 3.8 5.0 5.5 v i dd supply current v dd = 5 v - 21 30 ma v dd = 3.8 v - 16 25 ma inputs clk24, tch0 to tch7, taux, pwrdwn, ltclk, ltcnt0, ltcnt1, lten, pini and sbmclk v il low level input voltage -- 0.3v dd v v ih high level input voltage 0.7v dd -- v i i input current v i = 0 v; t amb = 25 c --- 10 m a v i = 5.5 v; t amb = 25 c -- 10 m a
february 1994 43 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 note 1. for applications requiring minimum power dissipation the device may be operated from a nominal +4 v supply. input reset v tlh threshold voltage low-high 0.8v dd -- v v thl threshold voltage high-low -- 0.2v dd v v hys hysteresis v tlh - v thl - 1.5 - v i i input current v i = v dd 25 - 400 m a outputs rasn, casn, wclock and wdata v ol low level output voltage i o = - 3ma -- 0.4 v v oh high level output voltage i o = 3 ma v dd - 0.5 -- v outputs ltref, wen, oen, a0 to a8, speed, spdf, pino1, pino3, azchk, test2, test3, mclk, sbef, sbdir and urda v ol low level output voltage i o = - 2ma -- 0.4 v v oh high level output voltage i o = 2 ma v dd - 0.5 -- v inputs/outputs d0 to d3; with outputs in 3-state v il low level input voltage ttl-level -- 0.8 v v ih high level input voltage ttl-level 2 -- v i i input leakage current v i = 0 v; t amb = 25 c --- 10 m a v i = 5.5 v; t amb = 25 c -- 10 m a inputs/outputs d0 to d3 v ol low level output voltage i o = - 3ma -- 0.4 v v oh high level output voltage i o = 3 ma v dd - 0.5 -- v inputs/outputs ltdata, sbcl, sbda and sbws; with outputs in 3-state v il low level input voltage ttl-level -- 0.3v dd v v ih high level input voltage ttl-level 0.7v dd -- v i i input leakage current v i = 0 v; t amb = 25 c --- 10 m a v i = 5.5 v; t amb = 25 c -- 10 m a inputs/outputs ltdata, sbcl, sbda and sbws v ol low level output voltage i o = - 3ma -- 0.4 v v oh high level output voltage i o = 3 ma v dd - 0.5 -- v symbol parameter conditions min. typ. max. unit
february 1994 44 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 ac characteristics v dd = 3.8 to 5.5 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit clock inputs c i input capacitance -- 10 pf clk24 f pulse frequency 23 24.576 26 mhz t l-i pulse width low 10 -- ns t h-i pulse width high 10 -- ns sbmclk f pulse frequency - 6.144 12.5 mhz t l-i pulse width low 30 -- ns t h-i pulse width high 30 -- ns clock outputs c l load capacitance -- 50 pf mclk f pulse frequency - 6.144 - mhz t l-i pulse width low 50 -- ns t h-i pulse width high 50 -- ns t dmfr delay time from clk24 note 1 -- 45 ns t d delay time from pwrdwn - 15 - ns clock inputs c i input capacitance -- 10 pf inputs ltclk, ltcnt0, ltcnt1, lten, reset, tch0 to tch7 and taux t sumr set-up time to mclk note 2 40 -- ns t hmr hold time from mclk note 2 0 -- ns input pini t sumr set-up time to mclk note 1 70 -- ns t hmr hold time from mclk note 1 0 -- ns outputs c l load capacitance -- 50 pf
february 1994 45 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 outputs a0 to a8, azchk, test2, ltref, sbdir, sbef, spdf, speed, pino1 to pino3, urda, wclock, wdata, oen and wen t dmr delay time from mclk note 2 -- 30 ns outputs oen and wen t d delay time from pwrdwn - 15 - ns output rasn t dfr delay time from clk24 note 1 -- 30 ns t d delay time from pwrdwn - 15 - ns output casn t dfr delay time from clk24 note 1 -- 30 ns t d delay time from pwrdwn - 15 - ns inputs/outputs c i input capacitance -- 10 pf c l load capacitance -- 50 pf inputs/outputs d0 to d3 t sucr set-up time to casn note 3 10 -- ns t hcr hold time from casn note 3 0 -- ns t dmr delay time from mclk note 2 -- 25 ns t d delay time from pwrdwn - 15 - ns input/output ltdata t sumr set-up time to mclk note 2 40 -- ns t hmr hold time from mclk note 2 0 -- ns t dmr delay time from mclk note 2 -- 30 ns t d delay time from pwrdwn - 15 - ns t d delay time from lten - 15 - ns inputs/outputs sbcl and sbws t sumr set-up time to mclk note 2 40 -- ns t hmr hold time from mclk note 2 0 -- ns t dsr delay time from sbmclk note 3 -- 40 ns t dmr delay time from mclk notes 2 and 5 -- 30 ns t d delay time from pwrdwn - 15 - ns symbol parameter conditions min. typ. max. unit
february 1994 46 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 notes 1. low-to-high transition of clk24. 2. low-to-high transition of mclk. 3. low-to-high transition of casn. 4. low-to-high transition of sbmclk. 5. 3-state control. input/output sbda t sumr set-up time to mclk note 2 40 -- ns t hmr hold time from mclk note 2 0 -- ns t dmr delay time from mclk note 2 -- 30 ns t d delay time from pwrdwn - 15 - ns symbol parameter conditions min. typ. max. unit fig.30 timing for ac characteristics. mea716 - 1 clk24 mclk out1 in1 out2 casn in2 sbmclk out3 t dfr dfr t hcr t sucr t t l?i h?i t dsr t dmr t hmr t sumr t h? t l? t dmfr t l? t h? t dfr t dmfr t
february 1994 47 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 package outline dimensions in mm. 1.55 0.85 mbc658 - 1 detail x 1.45 1.15 0.25 0.14 3.2 2.7 0 to 7 o 2.85 2.65 0.30 0.05 a b pin 1 index 19.2 18.2 1.2 0.8 (4x) 20.1 19.9 25.2 24.2 1.0 0.15 m b 0.50 0.35 1.2 0.8 (4x) 14.1 13.9 0.50 0.35 0.15 m a 1 64 52 51 33 32 20 19 1.0 s 0.15 s seating plane x fig.31 64-lead quad flat-pack; plastic (sot208).
philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 february 1994 48 soldering quad ?at-packs b ywave during placement and before soldering, the component must be fixed with a droplet of adhesive. after curing the adhesive, the component can be soldered. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 c within 6 s. typical dwell time is 4 s at 250 c. a modified wave soldering technique is recommended using two waves (dual-wave), in which, in a turbulent wave with high upward pressure is followed by a smooth laminar wave. using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. b y solder paste reflow reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. dwell times vary between 50 and 300 s according to method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 min at 45 c. r epairing soldered joints ( by hand-held soldering iron or pulse-heated solder tool ) fix the component by first soldering two, diagonally opposite, end pins. apply the heating tool to the flat part of the pin only. contact time must be limited to 10 s at up to 300 c. when using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 c. (pulse-heated soldering is not recommended for so packages.) for pulse-heated solder tool (resistance) soldering of vso packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
february 1994 49 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress rating only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. the digital compact cassette logo is a registered trade mark of philips electronics n.v.
february 1994 50 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 notes
february 1994 51 philips semiconductors product speci?cation tape formatting and error correction for the dcc system saa2022 notes
philips semiconductors philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40 783 749, fax. (31)40 788 399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970). tel. (011)829-1166, fax. (011)829-1849 canada: integrated circuits: tel. (800)234-7381, fax. (708)296-8556 discrete semiconductors: 601 milner ave, scarborough, ontario, m1b 1m8, tel. (0416)292 5161 ext. 2336, fax. (0416)292 4477 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 colombia: carrera 21 no. 56-17, bogota, d.e., p.o. box 77621, tel. (571)217 4609, fax. (01)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032)88 2636, fax. (031)57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (9)0-50261, fax. (9)0-520971 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01)4099 6161, fax. (01)4099 6427 germany: p.o. box 10 63 23, 20095 hamburg , tel. (040)3296-0, fax. (040)3296 213 greece: no. 15, 25th march street, gr 17778 tavros, tel. (01)4894 339/4894 911, fax. (01)4814 240 hong kong: 15/f philips ind. bldg., 24-28 kung yip st., kwai chung, tel. (0)4245 121, fax. (0)4806 960 india: peico electronics & electricals ltd., components dept., shivsagar estate, block 'a', dr. annie besant rd., worli, bombay 400 018, tel. (022)4938 541, fax. (022)4938 722 indonesia: philips house, jalan h.r. rasuna said kav. 3-4, p.o. box 4252, jakarta 12950, tel. (021)5201 122, fax. (021)5205 189 ireland: newstead, clonskeagh, dublin 14, tel. (01)640 000, fax. (01)640 200 italy: viale f. testi, 327, 20162 milano, tel. (02)6752.1, fax. (02)6752.3350 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, kokio 108, tel. (03)3740 5101, fax. (03)3740 0570 korea: (republic of) philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)794-5011, fax. (02)798-8022 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)757 5511, fax. (03)757 4880 mexico: philips components, 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, tel. (040)78 37 49, fax. (040)78 83 99 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (22)74 8000, fax. (22)74 8341 pakistan: philips markaz, m.a. jinnah rd., karachi 3, tel. (021)577 039, fax. (021)569 1832 philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 911, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: av. eng. duarte pacheco 6, 1009 lisboa codex, tel. (01)683 121, fax. (01)658 013 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: 195-215 main road, martindale, p.o. box 7430,johannesburg 2000, tel. (011)470-5433, fax. (011)470-5494 spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 7730 taiwan: 69, min sheng east road, sec 3, p.o. box 22978, taipei 10446, tel. (2)509 7666, fax. (2)500 5899 thailand: philips electronics (thailand) ltd., 60/14 moo 11, bangna - trad road km. 3 prakanong, bangkok 10260, tel. (2)399-3280 to 9, (2)398-2083, fax. (2)398-2080 turkey: talatpasa cad. no. 5, 80640 levent/istanbul, tel. (0212)279 2770, fax. (0212)269 3094 united kingdom: philips semiconductors limited, p.o. box 65, philips house, torrington place, london, wc1e 7hd, tel. (071)436 41 44, fax. (071)323 03 42 united states: integrated circuits: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 discrete semiconductors: 2001 west blue heron blvd., p.o. box 10330, riviera beach, florida 33404, tel. (800)447-3762 and (407)881-3200, fax. (407)881-3300 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 for all other countries apply to: philips semiconductors, international marketing and sales, building baf-1, p.o. box 218, 5600 md, eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd28 ? philips electronics n.v. 1994 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

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